Recently, in an active-matrix type display apparatus, so-called monolithic circuit techniques in which are formed on the same glass substrate a thin film transistor for pixels that is for injecting electric charges into the pixels; and a thin film transistor for peripheral circuits that makes up a peripheral circuit such as a drive circuit, etc., for driving a scan line or signal line which is connected to the thin film transistor for pixels are becoming popular.
In this type of display apparatuses, a scan-line drive circuit selects a display element which is arranged two-dimensionally in units of rows and writes a voltage in accordance with display data to the selected display element to display an image. As this scan line drive circuit, a shift register which successively shifts an output signal based on a clock signal is used. In a dot sequential driving display apparatus, a similar shift register is provided within a signal-line drive circuit for driving a drive signal.
When the shift register is used in the scan-line drive circuit and the signal-line drive circuit, at the time of turning on or off a power supply circuit of a liquid crystal display apparatus, an operation of the shift register may become unstable, causing disturbances of the image to occur. In this case, when an all-on operation which causes high-level output signals to be output simultaneously from all output terminals of the shift register, the disturbances of the image displayed on a screen may be alleviated. The shift register which makes it possible such an all-on operation is disclosed in WO2012/029799 (Patent document 1), for example.
FIG. 22 is a diagram showing an exemplary configuration of a shift register according to the related art disclosed in WO2012/029799. The shift register shown therein is includes multi-stage shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn (n is a natural number which is equal to 2 or more) connected in cascade. To each of the shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn are supplied clock signals CK1 and CK2 and all-on control signals AON and AONB (where AONB is an inverted signal of AON). Moreover, a start pulse signal ST is input to a set terminal SET of the first-stage shift register unit circuit SRU1 and an output terminal OUT of pre-stage shift register circuits SRU2, SRU3, . . . , SRUn is connected to each set terminal SET of the second-stage-and-thereafter shift register unit circuits SRU2, SRU3, . . . , SRUn. The individual output terminals OUTs of the shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn are respectively connected to scan lines GL1, GL2, GL3, . . . , GLn. The respective shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn have the same configuration.
Below, an arbitrary one of the shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn will be called “a shift register unit circuit SRU”.
FIG. 23 is a diagram showing an exemplary configuration of a related art shift register unit circuit SRU shown in the above-described FIG. 22. The shift register unit circuit SRU includes n-channel MOS (Metal Oxide Semiconductor) field-effect transistors (below-called “NMOS transistors”) Q1 to Q9, a resistor R1, and capacitors CA and CB. Of these, the NMOS transistors Q5, Q6, Q7; the resistor R1; and the capacitor CB make up a non-active output control unit SRUA; the NMOS transistors Q1, Q4, and Q8 make up an active output control unit SRUB, the NMOS transistors Q2, Q9, and the capacitor CA make up an active output unit SRUC, and the NMOS transistor Q3 makes up a non-active output unit SRUD. The active output control unit SRUB controls the active output unit SRUC to bring an output signal to a high level, while the non-active output control unit SRUA controls a non-active output unit SRUD to bring the output signal to a low level.
Of the multi-stage shift register unit circuits SRU1, SRU2, SRU3, SRUn, a clock signal CK1 and a clock signal CK2 are respectively input to a clock terminal CK and a clock terminal CKB of an odd-numbered stage shift register unit circuit SRU, and, in a manner which is converse from the odd-numbered stage shift register unit circuit, the clock signal CK2 and the clock signal CK1 are respectively input to the clock terminal CK and the clock terminal CKB of an even-numbered stage shift register unit circuit SRU. The clock signal CK1 and the clock signal CK2 are, for example, clock signals whose phases are mutually offset by 180°, and a low-level segment of each of the signals is set such that they do not take a high level at the same time. The phase difference between the clock signal CK1 and the clock signal CK2 is not to be limited to 180°, so that the clock signal CK1 and the clock signal CK2 may be arbitrary clock signals with the limit that high-level periods thereof do not overlap mutually.
Next, an operation of the above-described related art shift register is described. FIGS. 24A and 24B are timing charts for explaining an exemplary operation of the related art shift register, where FIG. 24A is a time chart at the time of a normal operation and FIG. 24B is a time chart at the time of an all-on operation. In FIGS. 24A and 24B, a high level and a low level of the start pulse signal ST and the clock signals CK1 and CK2 respectively correspond to a power supply voltage VDD supplied to the shift register and a ground voltage VSS. Moreover, in FIGS. 24A and 24B, N11 and N21 represent nodes N1 and N2 of the first-stage shift register unit circuit SRU1, N12 and N22 represent nodes N1 and N2 of the second-stage shift register unit circuit SRU2, N1n and N2n represent nodes N1 and N2 of the nth-stage shift register unit circuit SRUn, and OUT1, OUT2, and OUTn represent output signals of the first-stage, second-stage, and n-th stage shift register unit circuits SRUs.
First, the normal operation is explained. In the normal operation, the all-on control signal AON is set to a low level, and the all-on control signal AONB, which is an inverted signal thereof, is set to a high level. When the start pulse signal ST is input to the set terminal SET of the first-stage shift register unit circuit SRU1 at time to, in the active output control unit SRUB, the NMOS transistor Q1 is turned on and the node N11 is pre-charged to a voltage (VDD−Vth), which is a drop from the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor Q1.
In this case, in the non-active output control unit SRUA, the clock signal CK2 input to the clock terminal CKB and the start pulse signal ST input to the set terminal SET both take a high level, so that all of the NMOS transistors Q5, Q6, and Q7 are turned on. However, the resistor R1 is of a high resistance, so that the voltage of the node N21 takes a low level around the ground voltage VSS. In this way, the signal level of the gate of the NMOS transistors Q3 and Q4 takes a low level, so that the NMOS transistors Q3 and Q4 are both turned off.
Thereafter, when the respective signal levels of the clock signal CK2 input to the clock terminal CKB and the start pulse signal ST input to the set terminal SET take a low level of the ground voltage VSS, the NMOS transistors Q5 and Q7 are turned off, so that the node N21 takes a floating state, while the voltage of the node N21 is held by the capacitor CB. Moreover, when the signal level of the start pulse signal ST input to the set terminal SET takes a low level of the ground voltage VSS, the NOMS transistor is turned off, so that the node N11 takes a floating state, while the voltage of this node N11 is held by the capacitor CA.
Next, when the clock signal CK1 input to the clock terminal CK transitions to a high level at the time t1, the source voltage of the NMOS transistor Q2 rises. When the source voltage of the NMOS transistor Q2 rises, the voltage of the node N11 is pushed up, by the bootstrap effect by the capacitor CA, to a voltage which is higher than the power supply voltage VDD. When the gate voltage of the NMOS transistor Q2 takes a high voltage, the NMOS transistor Q2 passes on the high level of the clock signal CK1 input to the clock terminal CK to the output terminal OUT1. In this way, the output signal OUT1 takes a high level to be activated.
Thereafter, when the clock signal CK2 input to the clock terminal CKB transitions to a high level at the time t2, the NMOS transistor Q5 is turned to thereby cause the voltage of the node N21 to rise. When the voltage of the node N21 rises, the gate voltages of the NMOS transistor Q3 and the NMOS transistor Q4 rise and these NMOS transistors Q3 and Q4 are both turned on to simultaneous conduct discharging of the node N1 and pulling down of the output terminal OUT. In this way, the output signal OUT1 takes a low level to be deactivated. Thereafter, whenever the clock level of the clock signal CK2 which is input to the clock terminal CKB periodically takes a high level, the NMOS transistor Q5 is turned on to cause the signal level of the node N21 to maintained at a high level. As a result, at or after the time t2, the NMOS transistors Q3 and Q4 are both maintained on, while the output signal OUT1 is maintained at a low level.
The same also holds for the next-stage shift register unit circuit SRU2, so that, at the time t1, an output signal of the output terminal OUT1 of the first-stage shift register unit circuit SRU1 is input to the set terminal SET of the second-stage shift register unit circuit to cause a node N12 to be pre-charged. Then, at the time t2, an output signal OUT2 is output from the output terminal OUT of the second-stage shift register unit circuit SRU2 at the time t2. Then, when the clock signal CK1 transitions to a high level at the time t3, discharging of the node N12 in the second-stage shift register unit circuit SRU2 and pulling down of the output terminal OUT are conducted simultaneously, the output signal OUT2 takes a low level to be deactivated.
Below, the same operations are repeated up to the final-stage shift register unit circuit SRUn. As a result, the multiple shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn carry out the shift operation and successively output a high-level pulse signal to the scan lines GL1, GL2, GL3, . . . , GLn.
According to this shift register, a stable shift operation may be conducted using only two-phase clock signals CK1 and CK2 and a pre-stage output signal as input signals without producing a flow-through current.
Next, an all-on operation in which high-level output signals are output simultaneously from the all-output terminal OUT of the multiple shift register unit circuits SRU1, SRU2, SRU3, SRUn which make up the shift register are described.
To activate the all-on operation, an all-on control signal AON is set to a high level, while an all-on control signal AONB, which is an inverted signal thereof, is set to a low level. Moreover, in this example, the start pulse signal ST and the clock signals CK1 and CK2 are all set to a high level.
When the all-on control signal AON is set to a high level and the all-on control signal AONB is set to a low level, the NMOS transistor Q9 is turned on in the first-stage shift register unit circuit SRU1, while the NMOS transistor Q8 is turned off. Moreover, in this case, the NMOS transistor Q6 is turned off and the NMOS transistor Q7 is turned on, so that the node N21 takes a low level (a ground voltage VSS), while the NMOS transistor Q3 to which the gate is connected to the node N21 is turned off. In this way, no element exists which drives the output terminal OUT to a low level. When the NMOS transistor Q9 is turned on in such a state, a high-level output signal OUT1 is output to the output terminal OUT.
In the second-stage-and-thereafter shift register unit circuits SRU2, SRU3, . . . , SRUn, a high-level output signal from the pre-stage output terminal OUT is input to the SET terminal SET thereof, so that the second-stage-and-thereafter shift register unit circuit operates in the same manner as the first stage. Thus, an all-output signal which is output from the shift register unit circuits SRU1, SRU2, SRU3, . . . , SRUn to the scan lines GL1, GL2, GL3, . . . , GLn takes a high level to cause the all-on operation to be conducted.
Here, according to the technique disclosed in Patent document 1, when the start pulse signal ST input to the set terminal SET and the all-on control signal AON take a high level at the time of the all-on operation, the NMOS transistors Q5 and Q7 are both turned on, while the all-on control signal AONB takes a low level, and the NMOS transistor Q6 is turned off, so that a flow-through current within the non-active output control unit SRUA is shut off.
Moreover, when the all-on control signal AON takes a high level and the all-on control signal AONB takes a low level at the time of the all-on operation, the thin film transistor Q8 is turned off with the NMOS transistor Q6. In this way, the flow-through current within the active output control unit SRUB is shut off. Moreover, when the NMOS transistor Q6 is turned off, the signal level of the node N2 is brought to a low level by the NMOS transistor Q7 based on a signal input to the set terminal SET. When the signal level of the node N2 is brought to the low level, the NMOS transistor Q3 whose gate is connected to the node N2 is turned off, preventing a flow-through current from flowing through the NMOS transistors Q2 and Q3.